AI-Guided Hybrid Power Optimization for VLSI: Combining Clock Gating, Power Gating, DVFS, and MTCMOS in Embedded Systems

Abstract

The rapidly growing applications of embedded systems in mobile devices, Internet of Things (IoT), and wearables technologies now requires the design of low-power Very-Large-Scale Integration (VLSI) circuits to manage the power consumption demand of semiconductor devices used in different electronic circuits.To reduce power consumption and maintain system-level performance/functionalities in designing a VLSI circuits the various techniques are developed among those most effective are practice are: (1)Clock Gating, (2)Power Gating, (3) Dynamic Voltage and Frequency Scaling (DVFS), and (4)Multi-Threshold CMOS (MTCMOS).These techniques features in actively disabling of clock signal in the inactive portion of the circuit ,the isolation of inactive blocks,tweaks voltage and frequency to match workload demands to reduce dynamic power dissipation, minimizes leakage power (when the circuit is idle) by using transistors with different threshold voltages to minimize the power dissipation. However, the individual usage of these four techniques improves one parameter and disturb other parameters (for e.g. Clock Gatingsaves dynamic power but doesn’t help much with leakage.Power Gating saves leakage but increases area (extra sleep transistors) and can cause delay when waking up.DVFS reduces dynamic power but can reduce performance if voltage/frequency is lowered too much. MTCMOSreduces leakage but adds complexity/area overhead.). In order to overcome all above limitation this research paper proposes AI-driven hybrid power optimization framework that combine all above four technique and according to the system requirements use them independently or in combination. The Reinforcement learning (RL) AI model is used that monitors the system workload, switching activity, and thermal conditions and intelligently select the four techniques at the real time to have best possible energy efficiency results. The performance of the proposed framework is tested on VLSI-EDA tools (Synopsys-Primetime PX) to measure the dynamic power, leakage power, and performance/area trade-offs. The results shows that the proposed framework is a good indication for using in future embedded devices and can offer innovation opportunities as the AI based future innovation opportunities for low-power design techniques have become fundamental demand of VLSI designers due to the increase in energy-efficient demand.